Sigma-delta conversion has been generally understood for many years. Recent technological advances make devices utilizing sigma-delta conversion more attractive and their use is becoming more widespread. Sigma-delta converters are useful in such applications as communications systems and wireless Local Area Networks (LAN). These converters provide high dynamic range and flexibility in converting low bandwidth input signals. The general principle of the sigma-delta architecture is to make rough evaluations of the signal and to measure, integrate, and compensate for errors in the evaluation.
FIG. 1 shows a simple block diagram of a conventional first order sigma-delta Analog-to-Digital Converter (ADC) system 100. The sigma-delta converter 100 has two primary constituents: a sigma-delta modulator 102 and a digital filter 104. An input signal X is fed into the sigma-delta modulator 102, through a junction 106, and to an amplifying structure 108, such as an integrator, resonator, and/or passive structure (capacitor, resistor, inductor, and so forth). The amplifying structure 108 distributes the converter quantization error, or quantization noise, such that it is very low in the band of interest according to well known techniques. The amplifying structure 108 outputs a signal that is input to a comparator 110. This system (e.g. system 100) can act as a single-bit or multi-bit quantizer or ADC. The output of the comparator 110 is directed to a feedback Digital-to Analog Converter (DAC) 112, which outputs an analog approximation signal Q back to junction 106 as part of a feedback loop. The analog signal Q is subtracted at the junction from the analog input signal X in an attempt to reduce in-band quantization noise and to force the average of the signal Q to be equal to the input signal X. The resulting output signal is sent through the comparator 110 and provided as an output signal from the sigma-delta modulator 102 to the digital filter 104, which may be a decimation filter. The digital filter 104 outputs a digital signal Y with certain characteristics, such as desired bandwidth and so forth.
The first order sigma-delta converter 100 tends to have a high level of quantization noise when the analog signal is quantized. The quantization noise, or quantization error noise, limits the dynamic range of the first order sigma-delta converter 100. To decrease this noise, one or more additional amplifying structures may be added to create a high order sigma-delta converter. A sigma-delta converter having two amplifying structures is referred to as a second order converter, a converter having three amplifying structures is referred to as a third order converter, and so forth. Increasing the order of the converter and, thus, decreasing the quantization noise in the output signal, leads to certain benefits such as a higher input signal bandwidth, a reduced clock rate, and/or an increased output precision. However, higher order sigma-delta converters, particularly those with a single feedback loop, are prone to stability problems, which lead to undesired results such as a loss of a connection or a signal. Since stability also depends on input signal conditions, which are not always known, mathematical treatment and/or simulation do not lead to complete solutions.
There are several solutions known in the art to address the stability problem with high order sigma-delta converters. For example, the converter may be made more stable by designing it with a “less aggressive” noise shaping function. However, making the converter more stable in this manner increases quantization noise and reduces the Signal-to-Noise Ratio (SNR), which are undesired effects. Another option to increase the stability is through a process known as “graceful degradation.” According to the graceful degradation process, the order (e.g. the number of amplifying structures) of the loop is reduced based on the detection of overflow conditions in an effort to stabilize the signal. Usually, this approach is inaccurate and often requires complex and costly circuitry overhead. Another option quite often employed is the implementation of a “reset,” in which if an overflow condition or instability is detected, the circuit is reset by canceling out the signal at one or more amplifying structures. The sigma-delta conversion operation must then be reinitiated, which leads to a temporary loss of information. Such a loss of information is intolerable in many systems, such as LANs and other communication systems.